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ltc6910-1 ltc6910-2/ltc6910-3 1 6910123fa , ltc and lt are registered trademarks of linear technology corporation. n 3-bit digital gain control in three gain-code options n rail-to-rail input range n rail-to-rail output swing n single or dual supply: 2.7v to 10.5v total n 11mhz gain bandwidth product n input noise down to 8nv/ ? hz n system dynamic range to 120db n input offset voltage: 1.5mv n 8-pin low profile (1mm) sot-23 (thinsot?) package digitally controlled programmable gain amplifiers in sot-23 n data acquisition systems n dynamic gain changing n automatic ranging circuits n automatic gain control the ltc ? 6910 family are low noise digitally program- mable gain amplifiers (pgas) that are easy to use and occupy very little pc board space. the inverting gain is adjustable using a 3-bit digital input to select gains of 0, 1, 2, 5, 10, 20, 50 and 100v/v in the ltc6910-1; 0, 1, 2, 4, 8, 16, 32 and 64v/v in the ltc6910-2; and 0, 1, 2, 3, 4, 5,6 and 7v/v in the ltc6910-3. the ltc6910-xs are inverting amplifiers with rail-to-rail output. when operated with unity gain, they will also process rail-to-rail input signals. a half-supply reference generated internally at the agnd pin supports single power supply applications. operating from single or split supplies from 2.7v to 10.5v, the ltc6910-x family is offered in an 8-lead sot-23 package. single supply programmable amplifier frequency response (ltc6910-1) descriptio u features applicatio s u typical applicatio u 2 1 3 v in v out = gain ?v in agnd 1 f or larger pin 2 (agnd) provides built-in half-supply reference with internal resistance of 5k. agnd can also be driven by a system analog ground reference near half supply 6910 ta01 5 4 ltc6910-x 6 8 v + 2.7v to 10.5v 0.1 f g2 g1 g0 7 6910-1 0 ? ? ? ?0 ?0 ?0 100 6910-2 0 ? ? ? ? ?6 ?2 ?4 gain in volts/volt 6910-3 0 ? ? ? ? ? ? ? digital inputs g2 0 0 0 0 1 1 1 1 g1 0 0 1 1 0 0 1 1 g0 0 1 0 1 0 1 0 1 frequency (hz) 10 gain (db) 30 50 0 20 40 100 10k 100k 1m 10m 6910 ta01b C10 1k gain of 100 (digital input 111) gain of 1 (digital input 001) gain of 2 (digital input 010) gain of 5 (digital input 011) gain of 10 (digital input 100) gain of 20 (digital input 101) gain of 50 (digital input 110) v s = 10v, v in = 5mv rms thinsot is a trademark of linear technology corporation. u.s. patent number 6121908.
ltc6910-1 ltc6910-2/ltc6910-3 2 6910123fa total supply voltage (v+ to vC) ............................. 11v input current ..................................................... 25ma operating temperature range (note 2) ltc6910-1c, -2c, -3c ........................ C 40 c to 85 c ltc6910-1i, -2i, -3i ........................... C 40 c to 85 c ltc6910-1h, -2h, -3h .................... C 40 c to 125 c specified temperature range (note 3) ltc6910-1c, -2c, -3c ........................ C 40 c to 85 c ltc6910-1i, -2i, -3i ........................... C 40 c to 85 c ltc6910-1h, -2h, -3h .................... C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 150 c, q ja = 230 c/w ltc6910-1cts8 ltc6910-1its8 ltc6910-1hts8 ltc6910-2cts8 ltc6910-2its8 ltc6910-2hts8 ltc6910-3cts8 ltc6910-3its8 ltc6910-3hts8 (note 1) ts8 part marking* ltb5 (6910-1) ltacq (6910-2) ltacs (6910-3) absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grades are identified by a label on the shipping container. out 1 agnd 2 in 3 v C 4 8 v + 7 g2 6 g1 5 g0 top view ts8 package 8-lead plastic tsot-23 table 1. ltc6910-1 nominal nominal nominal linear input range (v p-p ) input voltage gain dual 5v single 5v single 3v impedance g2 g1 g0 volts/volt (db) supply supply supply (k w ) 0 0 0 0 C120 10 5 3 (open) 0 0 1 C1 0 10 5 3 10 0 1 0 C2 6 5 2.5 1.5 5 0 1 1 C5 14 2 1 0.6 2 1 0 0 C10 20 1 0.5 0.3 1 1 0 1 C20 26 0.5 0.25 0.15 1 1 1 0 C50 34 0.2 0.1 0.06 1 1 1 1 C100 40 0.1 0.05 0.03 1 gai setti gs a d properties u uu
ltc6910-1 ltc6910-2/ltc6910-3 3 6910123fa table 2. ltc6910-2 nominal nominal nominal linear input range (v p-p ) input voltage gain dual 5v single 5v single 3v impedance g2 g1 g0 volts/volt (db) supply supply supply (k w ) 0 0 0 0 C120 10 5 3 (open) 0 0 1 C1 0 10 5 3 10 0 1 0 C2 6 5 2.5 1.5 5 0 1 1 C4 12 2.5 1.25 0.75 2.5 1 0 0 C8 18.1 1.25 0.625 0.375 1.25 1 0 1 C16 24.1 0.625 0.313 0.188 1.25 1 1 0 C32 30.1 0.313 0.156 0.094 1.25 1 1 1 C64 36.1 0.156 0.078 0.047 1.25 gai setti gs a d properties u uu table 3. ltc6910-3 nominal nominal nominal linear input range (v p-p ) input voltage gain dual 5v single 5v single 3v impedance g2 g1 g0 volts/volt (db) supply supply supply (k w ) 0 0 0 0 C120 10 5 3 (open) 0 0 1 C1 0 10 5 3 10 0 1 0 C2 6 5 2.5 1.5 5 0 1 1 C3 9.5 3.33 1.67 1 3.3 1 0 0 C4 12 2.5 1.25 0.75 2.5 1 0 1 C5 14 2 1 0.6 2 1 1 0 C6 15.6 1.67 0.83 0.5 1.7 1 1 1 C7 16.9 1.43 0.71 0.43 1.4
ltc6910-1 ltc6910-2/ltc6910-3 4 6910123fa the l denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1 (digital inputs 001), r l = 10k to midsupply point, unless otherwise noted. electrical characteristics c, i suffixes h suffix parameter conditions min typ max min typ max unit specifications for the ltc6910-1, ltc6910-2 and ltc6910-3 total supply voltage l 2.7 10.5 2.7 10.5 v supply current v s = 2.7v, v in = 1.35v l 23 23 ma v s = 5v, v in = 2.5v l 2.4 3.5 2.4 3.5 ma v s = 5v, v in = 0v, pins 5, 6, 7 = C 5v or 5v l 3 4.5 3 4.5 ma v s = 5v, v in = 0v, pin 5 = 4.5v, l 3.5 4.9 3.5 4.9 ma pins 6, 7 = 0.5v (note 4) output voltage swing low (note 5) v s = 2.7v, r l = 10k to midsupply point l 12 30 12 30 mv v s = 2.7v, r l = 500 w to midsupply point l 50 100 50 100 mv v s = 5v, r l = 10k to midsupply point l 20 40 20 40 mv v s = 5v, r l = 500 w to midsupply point l 90 160 90 160 mv v s = 5v, r l = 10k to 0v l 30 50 30 50 mv v s = 5v, r l = 500 w to 0v l 180 250 180 270 mv output voltage swing high (note 5) v s = 2.7v, r l = 10k to midsupply point l 10 20 10 20 mv v s = 2.7v, r l = 500 w to midsupply point l 50 80 50 85 mv v s = 5v, r l = 10k to midsupply point l 10 30 10 30 mv v s = 5v, r l = 500 w to midsupply point l 80 150 80 150 mv v s = 5v, r l = 10k to 0v l 20 40 20 40 mv v s = 5v, r l = 500 w to 0v l 180 250 180 250 mv output short-circuit current (note 6) v s = 2.7v 27 27 ma v s = 5v 35 35 ma agnd open-circuit voltage v s = 5v l 2.45 2.5 2.55 2.45 2.5 2.55 v agnd rejection (i.e., common mode v s = 2.7v, v agnd = 1.1v to upper agnd limit l 55 80 50 80 db rejection or cmrr) v s = 5v, v agnd = C2.5v to 2.5v l 55 75 50 75 db power supply rejection ratio (psrr) v s = 2.7v to 5v l 60 80 60 80 db signal attenuation at gain = 0 setting gain = 0 (digital inputs 000), f = 20khz l C 122 C 122 db slew rate v s = 5v, v out = 2.8v p-p 12 12 v/ m s v s = 5v, v out = 2.8v p-p 16 16 v/ m s digital input high voltage v s = 2.7v l 2.43 2.43 v v s = 5v l 4.5 4.5 v v s = 5v l 4.5 4.5 v digital input low voltage v s = 2.7v l 0.27 0.27 v v s = 5v l 0.5 0.5 v v s = 5v l 0.5 0.5 v digital input leakage current magnitude v C (digital input) v + 22 m a
ltc6910-1 ltc6910-2/ltc6910-3 5 6910123fa the l denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1 (digital inputs 001), r l = 10k to midsupply point, unless otherwise noted. electrical characteristics ltc6910-1c/ltc6910-1i ltc6910-1h parameter conditions min typ max min typ max unit specifications for ltc6910-1 only voltage gain (note 7) v s = 2.7v, gain = 1, r l = 10k l C 0.05 0 0.07 C 0.06 0 0.07 db v s = 2.7v, gain = 1, r l = 500 w l C 0.1 C 0.02 0.06 C 0.12 C 0.02 0.08 db v s = 2.7v, gain = 2, r l = 10k l 5.96 6.02 6.08 5.96 6.02 6.08 db v s = 2.7v, gain = 5, r l = 10k l 13.85 13.95 14.05 13.83 13.95 14.05 db v s = 2.7v, gain = 10, r l = 10k l 19.7 19.9 20.1 19.7 19.9 20.1 db v s = 2.7v, gain = 10, r l = 500 w l 19.6 19.85 20.1 19.4 19.85 20.1 db v s = 2.7v, gain = 20, r l = 10k l 25.7 25.9 26.1 25.65 25.9 26.1 db v s = 2.7v, gain = 50, r l = 10k l 33.5 33.8 34.1 33.4 33.8 34.1 db v s = 2.7v, gain = 100, r l = 10k l 39 39.6 40.2 38.7 39.6 40.2 db v s = 2.7v, gain = 100, r l = 500 w l 37.4 39 40.1 36.4 39 40.1 db v s = 5v, gain = 1, r l = 10k l C 0.05 0 0.07 C 0.05 0 0.07 db v s = 5v, gain = 1, r l = 500 w l C 0.1 C 0.01 0.08 C 0.11 C 0.01 0.08 db v s = 5v, gain = 2, r l = 10k l 5.96 6.02 6.08 5.955 6.02 6.08 db v s = 5v, gain = 5, r l = 10k l 13.8 13.95 14.1 13.75 13.95 14.1 db v s = 5v, gain = 10, r l = 10k l 19.8 19.9 20.1 19.75 19.9 20.1 db v s = 5v, gain = 10, r l = 500 w l 19.6 19.85 20.1 19.45 19.85 20.1 db v s = 5v, gain = 20, r l = 10k l 25.8 25.9 26.1 25.70 25.9 26.1 db v s = 5v, gain = 50, r l = 10k l 33.5 33.8 34.1 33.4 33.8 34.1 db v s = 5v, gain = 100, r l = 10k l 39.3 39.7 40.1 39.1 39.7 40.1 db v s = 5v, gain = 100, r l = 500 w l 38 39.2 40.1 37 39.2 40.1 db v s = 5v, gain = 1, r l = 10k l C 0.05 0 0.07 C 0.05 0 0.07 db v s = 5v, gain = 1, r l = 500 w l C 0.1 C 0.01 0.08 C 0.1 C 0.01 0.08 db v s = 5v, gain = 2, r l = 10k l 5.96 6.02 6.08 5.96 6.02 6.08 db v s = 5v, gain = 5, r l = 10k l 13.80 13.95 14.1 13.80 13.95 14.1 db v s = 5v, gain = 10, r l = 10k l 19.8 19.9 20.1 19.75 19.9 20.1 db v s = 5v, gain = 10, r l = 500 w l 19.7 19.9 20.1 19.6 19.9 20.1 db v s = 5v, gain = 20, r l = 10k l 25.8 25.95 26.1 25.75 25.95 26.1 db v s = 5v, gain = 50, r l = 10k l 33.7 33.85 34 33.6 33.85 34 db v s = 5v, gain = 100, r l = 10k l 39.4 39.8 40.2 39.25 39.8 40.2 db v s = 5v, gain = 100, r l = 500 w l 38.8 39.6 40.1 38 39.6 40.1 db offset voltage magnitude (internal op amp) l 1.5 9 1.5 11 mv (v os(oa) ) (note 8) offset voltage drift (internal op amp) (note 8) 6 8 m v/ c offset voltage magnitude gain = 1 l 3 15 3 18 mv (referred to in pin) (v os(in) ) gain = 10 l 1.7 10 1.7 12 mv dc input resistance (note 9) dc v in = 0v gain = 0 >100 >100 m w gain = 1 l 10 10 k w gain = 2 l 55k w gain = 5 l 22k w gain = 10, 20, 50, 100 l 11k w
ltc6910-1 ltc6910-2/ltc6910-3 6 6910123fa the l denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1 (digital inputs 001), r l = 10k to midsupply point, unless otherwise noted. electrical characteristics ltc6910-1c/ltc6910-1i ltc6910-1h parameter conditions min typ max min typ max unit specifications for ltc6910-1 only dc small-signal output resistance gain = 0 0.4 0.4 w gain = 1 0.7 0.7 w gain = 2 1 1 w gain = 5 1.9 1.9 w gain = 10 3.4 3.4 w gain = 20 6.4 6.4 w gain = 50 15 15 w gain = 100 30 30 w gain-bandwidth product gain = 100, f in = 200khz 8 11 14 8 11 14 mhz l 6 11 16 5 11 16 mhz wideband noise (referred to input) f = 1khz to 200khz gain = 0 output noise 3.8 3.8 m v rms gain = 1 10.7 10.7 m v rms gain = 2 7.3 7.3 m v rms gain = 5 5.2 5.2 m v rms gain = 10 4.5 4.5 m v rms gain = 20 4.2 4.2 m v rms gain = 50 3.9 3.9 m v rms gain = 100 3.4 3.4 m v rms voltage noise density (referred to input) f = 50khz gain = 1 24 24 nv/ ? hz gain = 2 16 16 nv/ ? hz gain = 5 12 12 nv/ ? hz gain = 10 10 10 nv/ ? hz gain = 20 9.4 9.4 nv/ ? hz gain = 50 8.7 8.7 nv/ ? hz gain = 100 7.6 7.6 nv/ ? hz total harmonic distortion gain = 10, f in = 10khz, v out = 1v rms C90 C90 db 0.003 0.003 % gain = 10, f in = 100khz, v out = 1v rms C77 C77 db 0.014 0.014 % agnd (common mode) input voltage range v s = 2.7v l 0.55 1.6 0.7 1.5 v (note 10) v s = 5v l 0.7 3.65 1 3.25 v v s = 5v l C 4.3 3.5 C 4.3 3.35 v
ltc6910-1 ltc6910-2/ltc6910-3 7 6910123fa the l denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1 (digital inputs 001), r l = 10k to midsupply point, unless otherwise noted. electrical characteristics ltc6910-2c/ltc6910-2i ltc6910-2h parameter conditions min typ max min typ max unit specifications for ltc6910-2 only voltage gain (note 7) v s = 2.7v, gain = 1, r l = 10k l C 0.06 0 0.08 C 0.07 0 0.08 db v s = 2.7v, gain = 1, r l = 500 w l C 0.1 C 0.02 0.06 C 0.11 C 0.02 0.06 db v s = 2.7v, gain = 2, r l = 10k l 5.96 6.02 6.1 5.95 6.02 6.1 db v s = 2.7v, gain = 4, r l = 10k l 11.9 12.02 12.12 11.9 12.02 12.12 db v s = 2.7v, gain = 8, r l = 10k l 17.8 17.98 18.15 17.8 17.98 18.15 db v s = 2.7v, gain = 8, r l = 500 w l 17.65 17.95 18.15 17.55 17.95 18.15 db v s = 2.7v, gain = 16, r l = 10k l 23.75 24 24.2 23.75 24 24.2 db v s = 2.7v, gain = 32, r l = 10k l 29.7 30 30.2 29.65 30 30.2 db v s = 2.7v, gain = 64, r l = 10k l 35.3 35.75 36.2 35.2 35.75 36.2 db v s = 2.7v, gain = 64, r l = 500 w l 34.2 35.3 36.2 33.7 35.3 36.2 db v s = 5v, gain = 1, r l = 10k l C 0.06 0 0.08 C 0.06 0 0.08 db v s = 5v, gain = 1, r l = 500 w l C 0.1 C 0.01 0.08 C 0.11 C 0.01 0.08 db v s = 5v, gain = 2, r l = 10k l 5.96 6.02 6.1 5.96 6.02 6.1 db v s = 5v, gain = 4, r l = 10k l 11.85 12.02 12.15 11.85 12.02 12.15 db v s = 5v, gain = 8, r l = 10k l 17.85 18 18.15 17.85 18 18.15 db v s = 5v, gain = 8, r l = 500 w l 17.65 17.9 18.15 17.6 17.9 18.15 db v s = 5v, gain = 16, r l = 10k l 23.85 24 24.15 23.78 24 24.15 db v s = 5v, gain = 32, r l = 10k l 29.7 30 30.2 29.7 30 30.2 db v s = 5v, gain = 64, r l = 10k l 35.6 35.9 36.2 35.5 35.9 36.2 db v s = 5v, gain = 64, r l = 500 w l 34.8 35.5 36 34.2 35.5 36 db v s = 5v, gain = 1, r l = 10k l C 0.05 0 0.07 C 0.05 0 0.07 db v s = 5v, gain = 1, r l = 500 w l C 0.1 C 0.01 0.08 C 0.1 C 0.01 0.08 db v s = 5v, gain = 2, r l = 10k l 5.96 6.02 6.1 5.96 6.02 6.1 db v s = 5v, gain = 4, r l = 10k l 11.9 12.02 12.15 11.9 12.02 12.15 db v s = 5v, gain = 8, r l = 10k l 17.85 18 18.15 17.85 18 18.15 db v s = 5v, gain = 8, r l = 500 w l 17.80 17.95 18.1 17.72 17.95 18.1 db v s = 5v, gain = 16, r l = 10k l 23.85 24 24.15 23.8 24 24.15 db v s = 5v, gain = 32, r l = 10k l 29.85 30 30.15 29.78 30 30.15 db v s = 5v, gain = 64, r l = 10k l 35.7 35.95 36.2 35.7 35.95 36.2 db v s = 5v, gain = 64, r l = 500 w l 35.2 35.8 36.2 34.8 35.8 36.2 db offset voltage magnitude (internal op amp) l 1.5 9 1.5 11 mv (v os(oa) ) (note 8) offset voltage drift (internal op amp) (note 8) l 68 m v/ c offset voltage magnitude gain = 1 l 3 15 3 17 mv (referred to in pin) (v os(in) ) gain = 8 l 2 10 2 12 mv dc input resistance (note 9) dc v in = 0v gain = 0 >100 >100 m w gain = 1 l 10 10 k w gain = 2 l 55k w gain = 4 l 2.5 2.5 k w gain = 8, 16, 32, 64 l 1.25 1.25 k w
ltc6910-1 ltc6910-2/ltc6910-3 8 6910123fa the l denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1 (digital inputs 001), r l = 10k to midsupply point, unless otherwise noted. electrical characteristics ltc6910-2c/ltc6910-2i ltc6910-2h parameter conditions min typ max min typ max unit specifications for ltc6910-2 only dc small-signal output resistance gain = 0 0.4 0.4 w gain = 1 0.7 0.7 w gain = 2 1 1 w gain = 4 1.6 1.6 w gain = 8 2.8 2.8 w gain = 16 5 5 w gain = 32 10 10 w gain = 64 20 20 w gain-bandwidth product gain = 64, f in = 200khz 9 13 16 9 13 16 mhz l 7 13 19 7 13 19 mhz wideband noise (referred to input) f = 1khz to 200khz gain = 0 output noise 3.8 3.8 m v rms gain = 1 10.7 10.7 m v rms gain = 2 7.3 7.3 m v rms gain = 4 5.3 5.3 m v rms gain = 8 4.6 4.6 m v rms gain = 16 4.2 4.2 m v rms gain = 32 4 4 m v rms gain = 64 3.6 3.6 m v rms voltage noise density (referred to input) f = 50khz gain = 1 24 24 nv/ ? hz gain = 2 16 16 nv/ ? hz gain = 4 12 12 nv/ ? hz gain = 8 10.3 10.3 nv/ ? hz gain = 16 9.4 9.4 nv/ ? hz gain = 32 9 9 nv/ ? hz gain = 64 8.1 8.1 nv/ ? hz total harmonic distortion gain = 8, f in = 10khz, v out = 1v rms C90 C90 db 0.003 0.003 % gain = 8, f in = 100khz, v out = 1v rms C77 C77 db 0.014 0.014 % agnd (common mode) input voltage range v s = 2.7v l 0.85 1.55 0.85 1.55 v (note 10) v s = 5v l 0.7 3.6 0.7 3.6 v v s = 5v l C 4.3 3.4 C 4.3 3.4 v
ltc6910-1 ltc6910-2/ltc6910-3 9 6910123fa the l denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1 (digital inputs 001), r l = 10k to midsupply point, unless otherwise noted. electrical characteristics ltc6910-3c/ltc6910-3i ltc6910-3h parameter conditions min typ max min typ max unit specifications for ltc6910-3 only voltage gain (note 7) v s = 2.7v, gain = 1, r l = 10k l C 0.05 0 0.07 C 0.05 0 0.09 db v s = 2.7v, gain = 1, r l = 500 w l C 0.1 C 0.02 0.06 C 0.11 C 0.02 0.06 db v s = 2.7v, gain = 2, r l = 10k l 5.93 6.02 6.08 5.93 6.02 6.09 db v s = 2.7v, gain = 3, r l = 10k l 9.35 9.5 9.7 9.35 9.5 9.75 db v s = 2.7v, gain = 4, r l = 10k l 11.9 11.98 12.2 11.9 11.98 12.2 db v s = 2.7v, gain = 4, r l = 500 w l 11.8 11.98 12.2 11.75 11.98 12.2 db v s = 2.7v, gain = 5, r l = 10k l 13.85 13.92 14.05 13.8 13.92 14.05 db v s = 2.7v, gain = 6, r l = 10k l 15.4 15.5 15.6 15.4 15.5 15.6 db v s = 2.7v, gain = 7, r l = 10k l 16.7 16.85 17 16.7 16.85 17 db v s = 2.7v, gain = 7, r l = 500 w l 16.55 16.8 17 16.47 16.8 17 db v s = 5v, gain = 1, r l = 10k l C 0.05 0 0.07 C 0.05 0 0.07 db v s = 5v, gain = 1, r l = 500 w l C 0.1 C 0.01 0.08 C 0.1 C 0.01 0.08 db v s = 5v, gain = 2, r l = 10k l 5.96 6.02 6.08 5.96 6.02 6.08 db v s = 5v, gain = 3, r l = 10k l 9.45 9.54 9.65 9.45 9.54 9.65 db v s = 5v, gain = 4, r l = 10k l 11.85 12.02 12.15 11.85 12.02 12.15 db v s = 5v, gain = 4, r l = 500 w l 11.8 11.95 12.15 11.75 11.95 12.15 db v s = 5v, gain = 5, r l = 10k l 13.8 13.95 14.05 13.8 13.95 14.05 db v s = 5v, gain = 6, r l = 10k l 15.35 15.5 15.65 15.35 15.5 15.65 db v s = 5v, gain = 7, r l = 10k l 16.7 16.85 17 16.7 16.85 17 db v s = 5v, gain = 7, r l = 500 w l 16.6 16.8 17 16.5 16.8 17 db v s = 5v, gain = 1, r l = 10k l C 0.06 0 0.07 C 0.06 0 0.07 db v s = 5v, gain = 1, r l = 500 w l C 0.1 C 0.01 0.08 C 0.12 C 0.01 0.08 db v s = 5v, gain = 2, r l = 10k l 5.96 6.02 6.08 5.96 6.02 6.08 db v s = 5v, gain = 3, r l = 10k l 9.4 9.54 9.65 9.4 9.54 9.65 db v s = 5v, gain = 4, r l = 10k l 11.85 12 12.2 11.85 12 12.2 db v s = 5v, gain = 4, r l = 500 w l 11.8 12 12.2 11.8 12 12.2 db v s = 5v, gain = 5, r l = 10k l 13.8 13.95 14.1 13.8 13.95 14.1 db v s = 5v, gain = 6, r l = 10k l 15.35 15.5 15.7 15.35 15.5 15.7 db v s = 5v, gain = 7, r l = 10k l 16.7 16.85 17.05 16.7 16.85 17.05 db v s = 5v, gain = 7, r l = 500 w l 16.65 16.8 17 16.6 16.8 17 db offset voltage magnitude (internal op amp) l 1.5 8 1.5 8 mv (v os(oa) ) (note 8) offset voltage drift (internal op amp) (note 8) l 68 m v/ c offset voltage magnitude gain = 1 l 3 15 3 15 mv (referred to in pin) (v os(in) ) gain = 4 l 1.9 10 1.9 10 mv dc input resistance (note 9) dc v in = 0v gain = 0 >100 >100 m w gain = 1 l 10 10 k w gain = 2 l 55k w gain = 3 l 3.3 3.3 k w gain = 4 l 2.5 2.5 k w gain = 5 l 22k w gain = 6 l 1.7 1.7 k w gain = 7 l 1.4 1.4 k w
ltc6910-1 ltc6910-2/ltc6910-3 10 6910123fa dc small-signal output resistance gain = 0 0.4 0.4 w gain = 1 0.7 0.7 w gain = 2 1 1 w gain = 3 1.3 1.3 w gain = 4 1.6 1.6 w gain = 5 1.9 1.9 w gain = 6 2.2 2.2 w gain = 7 2.5 2.5 w gain-bandwidth product gain = 7, f in = 200khz l 11 11 mhz wideband noise (referred to input) f = 1khz to 200khz gain = 0 output noise 3.8 3.8 m v rms gain = 1 10.7 10.7 m v rms gain = 2 7.3 7.3 m v rms gain = 3 6.1 6.1 m v rms gain = 4 5.3 5.3 m v rms gain = 5 5.2 5.2 m v rms gain = 6 4.9 4.9 m v rms gain = 7 4.7 4.7 m v rms voltage noise density (referred to input) f = 50khz gain = 1 24 24 nv/ ? hz gain = 2 16 16 nv/ ? hz gain = 3 14 14 nv/ ? hz gain = 4 12 12 nv/ ? hz gain = 5 11.6 11.6 nv/ ? hz gain = 6 11.2 11.2 nv/ ? hz gain = 7 10.5 10.5 nv/ ? hz total harmonic distortion gain = 4, f in = 10khz, v out = 1v rms C 90 C 90 db 0.003 0.003 % gain = 4, f in = 100khz, v out = 1v rms C 80 C 80 db 0.01 0.01 % agnd (common mode) input voltage range v s = 2.7v l 0.85 1.55 0.85 1.55 v (note 10) v s = 5v l 0.7 3.6 0.7 3.6 v v s = 5v l C 4.3 3.4 C 4.3 3.4 v electrical characteristics the l denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1 (digital inputs 001), r l = 10k to midsupply point, unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the ltc6910-xc and ltc6910-xi are guaranteed functional over the operating temperature range of C 40 c to 85 c. the ltc6910-xh are guaranteed functional over the operating temperature range of C40 c to 125 c. note 3: the ltc6910-xc are guaranteed to meet specified performance from 0 c to 70 c. the ltc6910-xc are designed, characterized and expected to meet specified performance from C 40 c to 85 c but are not tested or qa sampled at these temperatures. ltc6910-xi are guaranteed to meet specified performance from C 40 c to 85 c. the ltc6910-xh are guaranteed to meet specified performance from C 40 c to 125 c. note 4: operating all three logic inputs at 0.5v causes the supply current to increase typically 0.1ma from this specification. note 5: output voltage swings are measured as differences between the output and the respective supply rail. note 6: extended operation with output shorted may cause junction temperature to exceed the 150 c limit and is not recommended. note 7: gain is measured with a dc large-signal test using an output excursion between approximately 30% and 70% of supply voltage. note 8: offset voltage referred to in pin is (1 + 1/g) times offset voltage of the internal op amp, where g is nominal gain magnitude. see applica- tions information. note 9: input resistance can vary by approximately 30% part-to-part at a given gain setting. note 10: at limits of agnd input range, open-loop gain of internal op amp may be greater than, or as much as 15db below, its value at nominal agnd value. ltc6910-3c/ltc6910-3i ltc6910-3h parameter conditions min typ max min typ max unit specifications for ltc6910-3 only
ltc6910-1 ltc6910-2/ltc6910-3 11 6910123fa typical perfor a ce characteristics uw ltc6910-1 output voltage swing vs load current temperature ( c) 0.2 gain change (db) 0.1 0 0.1 0.2 6910 g01 50 0 50 150 100 gain = 100 gain = 10 gain = 1 v s = 2.5v output unloaded frequency (hz) 10 gain (db) 30 50 0 20 40 100 10k 100k 1m 10m 6910 g02 C10 1k gain of 100 gain of 1 gain of 2 gain of 5 gain of 10 gain of 20 gain of 50 v s = 5v, v in = 5mv rms gain 1 0 ?db frequency (mhz) 2.0 4.0 8.0 7.5 7.0 6.5 5.5 5.0 4.5 3.5 3.0 2.5 1.5 1.0 0.5 10 100 6910 g03 6.0 v in = 5mv rms v s = 2.7v v s = 5v ltc6910-1 frequency response ltc6910-1 C3db bandwidth vs gain setting ltc6910-1 power supply rejection vs frequency ltc6910-1 noise density vs frequency output current (ma) output votlage swing (v) (referred to supply voltage) +v s ? s 0.01 1 10 100 6910 g04 0.1 +v s ?0.5 ? s + 0.5 +v s ?1.0 ? s + 1.0 +v s ?1.5 ? s + 1.5 +v s ?2.0 ? s + 2.0 v s = 2.5v 125 c 25 c 40 c source sink frequency (khz) 20 rejection (db) 80 90 10 0 70 40 60 50 30 0.1 10 100 1000 6910 g05 1 +supply supply v s = 2.5v gain = 1 frequency (khz) 1 10 100 6910 g06 1 10 100 gain = 1 gain = 10 gain = 100 input-referred v s = 2.5v t a = 25 c voltage noise density (nv/ hz) ltc6910-1 distortion with light loading (r l = 10k) ltc6910-1 thd + noise vs input voltage frequency (khz) 0 ?0 ?0 ?0 150 6910 g07 ?0 ?0 50 100 gain = 100 gain = 10 gain = 1 200 ?0 ?00 ?0 0.1 0.3 3 0.03 0.01 0.003 0.001 1 thd (amplitude below fundamental) (db) thd (%) v s = 2.5v v out = 1v rms (2.83v p-p ) thd measures hd2 and hd3 frequency (khz) 0 ?0 ?0 ?0 150 6910 g08 ?0 ?0 50 100 gain = 100 gain = 10 gain = 1 200 ?0 ?00 ?0 0.1 0.3 3 0.03 0.01 0.003 0.001 1 thd (amplitude below fundamental) (db) thd (%) v s = 2.5v v out = 1v rms (2.83v p-p ) thd measures hd2 and hd3 input voltage (v p-p ) 0.01 ?0 (thd + noise)/signal (db) ?0 ?0 ?0 ?0 0.1 1 10 6910 g09 ?0 ?0 ?00 ?10 ?0 f in = 1khz v s = 5v noise bw = 22khz gain setting = 100 gain setting = 10 gain setting = 1 ltc6910-1 distortion with heavy loading (r l = 500 w ) ltc6910-1 gain shift vs temperature (ltc6910-1)
ltc6910-1 ltc6910-2/ltc6910-3 12 6910123fa typical perfor a ce characteristics uw ltc6910-2 output voltage swing vs load current temperature ( c) 0.2 gain change (db) 0.1 0 0.1 0.2 6910 g10 50 0 50 150 100 gain = 64 gain = 8 gain = 1 v s = 2.5v output unloaded frequency (hz) 10 gain (db) 30 50 0 20 40 100 1k 100k 1m 10m 6910 g11 ?0 10k v s = 5v v in = 10mv rms gain of 64 gain of 32 gain of 16 gain of 4 gain of 8 gain of 2 gain of 1 gain 1 0 ?db frequency (mhz) 2.0 4.0 8.0 7.5 7.0 6.5 5.5 5.0 4.5 3.5 3.0 2.5 1.5 1.0 0.5 10 100 6910 g12 6.0 v in = 10mv rms v s = 2.7v v s = 5v ltc6910-2 frequency response ltc6910-2 C3db bandwidth vs gain setting ltc6910-2 power supply rejection vs frequency ltc6910-2 noise density vs frequency output current (ma) output votlage swing (v) (referred to supply voltage) +v s ? s 0.01 1 10 100 6910 g13 0.1 +v s ?0.5 ? s + 0.5 +v s ?1.0 ? s + 1.0 +v s ?1.5 ? s + 1.5 +v s ?2.0 ? s + 2.0 v s = 2.5v 125 c 25 c 40 c source sink frequency (khz) 20 rejection (db) 80 90 10 0 70 40 60 50 30 0.1 10 100 1000 6910 g14 1 +supply Csupply v s = 2.5v gain = 1 frequency (khz) 1 10 100 6910 g15 1 10 100 gain = 1 gain = 8 gain = 64 input-referred v s = 2.5v t a = 25 c voltage noise density (nv/ hz) ltc6910-2 distortion with light loading (r l = 10k) ltc6910-2 thd + noise vs input voltage frequency (khz) 0 ?0 ?0 ?0 150 6910 g16 ?0 ?0 50 100 gain = 64 gain = 8 gain = 1 200 ?0 ?00 ?0 0.1 0.3 3 0.03 0.01 0.003 0.001 1 thd (amplitude below fundamental) (db) thd (%) v s = 2.5v v out = 1v rms (2.83v p-p ) thd measures hd2 and hd3 frequency (khz) 0 ?0 ?0 ?0 150 6910 g17 ?0 ?0 50 100 gain = 64 gain = 8 gain = 1 200 ?0 ?00 ?0 0.1 0.3 3 0.03 0.01 0.003 0.001 1 thd (amplitude below fundamental) (db) thd (%) v s = 2.5v v out = 1v rms (2.83v p-p ) thd measures hd2 and hd3 input voltage (v p-p ) 0.01 ?0 (thd + noise)/signal (db) ?0 ?0 ?0 ?0 0.1 1 10 6910 g18 ?0 ?0 ?00 ?10 ?0 f in = 1khz v s = 5v noise bw = 22khz gain setting = 64 gain setting = 8 gain setting = 1 ltc6910-2 distortion with heavy loading (r l = 500 w ) ltc6910-2 gain shift vs temperature (ltc6910-2)
ltc6910-1 ltc6910-2/ltc6910-3 13 6910123fa typical perfor a ce characteristics uw ltc6910-3 output voltage swing vs load current temperature ( c) 0.02 gain change (db) 0.01 0 0.01 0.02 6910 g19 50 0 50 150 100 gain = 7 gain = 4 gain = 1 v s = 2.5v output unloaded frequency (hz) 0 gain (db) 10 20 ? 5 15 1k 100 100k 1m 10m 6910 g20 ?0 10k gain of 7 gain of 6 gain of 5 gain of 4 gain of 3 gain of 2 gain of 1 v s = 5v v in = 10mv rms gain 0 C3db frequency (mhz) 2.0 4.0 8.0 7.0 5.0 3.0 1.0 6910 g21 6.0 v in = 10mv rms v s = 2.7v v s = 5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 13 10 245 6 78 9 ltc6910-3 frequency response ltc6910-3 C3db bandwidth vs gain setting ltc6910-3 power supply rejection vs frequency ltc6910-3 noise density vs frequency output current (ma) output votlage swing (v) (referred to supply voltage) +v s ? s 0.01 1 10 100 6910 g22 0.1 +v s ?0.5 ? s + 0.5 +v s ?1.0 ? s + 1.0 +v s ?1.5 ? s + 1.5 +v s ?2.0 ? s + 2.0 v s = 2.5v 125 c 25 c 40 c source sink frequency (khz) 20 rejection (db) 80 90 10 0 70 40 60 50 30 0.1 10 100 1000 6910 g23 1 +supply Csupply v s = 2.5v gain = 1 frequency (khz) 1 10 100 6910 g24 1 10 100 gain = 1 gain = 4 gain = 7 input-referred v s = 2.5v t a = 25 c voltage noise density (nv/ hz) ltc6910-3 distortion with light loading (r l = 10k) ltc6910-3 thd + noise vs input voltage frequency (khz) 0 ?0 ?0 ?0 150 6910 g25 ?0 ?0 50 100 200 ?0 ?00 ?0 0.1 0.3 3 0.03 0.01 0.003 0.001 1 thd (amplitude below fundamental) (db) thd (%) v s = 2.5v v out = 1v rms (2.83v p-p ) thd measures hd2 and hd3 gain = 7 gain = 1 gain = 4 frequency (khz) 0 C60 C50 C30 150 6910 g26 C70 C80 50 100 gain = 7 gain = 1 200 C90 C100 C40 0.1 0.3 3 0.03 0.01 0.003 0.001 1 thd (amplitude below fundamental) (db) thd (%) v s = 2.5v v out = 1v rms (2.83v p-p ) thd measures hd2 and hd3 gain = 4 input voltage (v p-p ) 0.01 ?0 (thd + noise)/signal (db) ?0 ?0 ?0 ?0 0.1 1 10 6910 g27 ?0 ?0 ?00 ?10 ?0 f in = 1khz v s = 5v noise bw = 22khz gain setting = 7 gain setting = 4 gain setting = 1 ltc6910-3 distortion with heavy loading (r l = 500 w ) ltc6910-3 gain shift vs temperature (ltc6910-3)
ltc6910-1 ltc6910-2/ltc6910-3 14 6910123fa out (pin 1): analog output. this is the output of an internal operational amplifier and swings to near the power supply rails (v + and v C ) as specified in the electrical characteristics table. the internal op amp remains active at all times, including the zero gain setting (digital input 000). as with other amplifier circuits, loading the output as lightly as possible will minimize signal distortion and gain error. the electrical characteristics table shows perfor- mance at output currents up to 10ma and current limits that occur when the output is shorted to midsupply at 2.7v and 5v supplies. signal outputs above 10ma are pos- sible but current-limiting circuitry will begin to affect amplifier performance at approximately 20ma. long-term operation above 20ma output is not recommended. do not exceed maximum junction temperature of 150 c. the output will drive capacitive loads up to 50pf. capacitances higher than 50pf should be isolated by a series resistor to preserve ac stability. agnd (pin 2): analog ground. the agnd pin is at the midpoint of an internal resistive voltage divider, develop- ing a potential halfway between the v + and v C pins, with an equivalent series resistance to the pin of nominally 5k w (figure 4). agnd is also the noninverting input of the internal op amp, which makes it the ground reference voltage for the in and out pins. because of this, very clean grounding is important, including an analog ground plane surrounding the package. recommended analog ground plane connection depends on how power is applied to the ltc6910-x (figures 1, 2, and 3). single power supply applications typically use v C for the system signal ground. the analog ground plane in single-supply applications should therefore tie to v C , and the agnd pin should be bypassed to this ground plane by a high quality capacitor of at least 1 m f (figure 1). the agnd pin then provides an internal analog reference voltage at half the supply voltage (with internal resistance of approximately 5k w ) which is the center of the swing range for both input and output. dual supply applications with symmetrical supplies (such as 5v) have a natural system ground at zero volts, which can drive the analog ground plane; agnd then connects directly to the ground plane, making zero volts the input and output reference voltage for the ltc6910-x (figure 2). finally, if a dual power supply is asymmetrical, the supply ground is still the natural ground plane voltage. to maximize signal swing capability with an asymmetrical supply, however, it is often desirable to refer the ltc6910-xs analog input and output to a voltage equidistant from the two supply rails v + and v C . the agnd pin will provide such a potential when open-circuited and bypassed with a capacitor (fig- ure 3), just as with a single power supply, but now the ground plane connection is different and the ltc6910-xs v + and v C pins are both isolated from this ground plane. uu u pi fu ctio s ltc6910-x digital ground plane (if any) analog ground plane 1 single-point system ground 234 reference v + 2 6910 f01 8765 0.1 f v + 1 f ltc6910-x digital ground plane (if any) analog ground plane 1 single-point system ground 234 6910 f02 8765 0.1 f v + 0.1 f v figure 2. symmetrical dual supply ground plane connection figure 1. single supply ground plane connection ltc6910-x digital ground plane (if any) analog ground plane 1 single-point system ground 234 6910 f03 8765 0.1 f v + 0.1 f 1 f v C mid-supply reference figure 3. asymmetrical dual supply ground plane connection
ltc6910-1 ltc6910-2/ltc6910-3 15 6910123fa + input r array feedback r array v 6910 f04 out v + 10k mos-input op amp in agnd 10k 2 v 4 v + 8 g1 g2 g0 1 3 cmos logic 6 7 5 figure 4. block diagram uu u pi fu ctio s where agnd does not connect to a ground plane, as in figures 1 and 3, it is important to ac-bypass the agnd pin. this is especially true when agnd is used as a reference voltage for other circuitry. also, without a bypass capaci- tor, wideband noise will enter the signal path from the internal voltage divider resistors that set the dc voltage on agnd. this noise can reduce snr by 3db at high gain settings. the resistors present a thvenin equivalent of approximately 5k to the agnd pin. an external capacitor from agnd to the ground plane, whose impedance is well below 5k at frequencies of interest, will suppress this noise. a 1 m f high quality capacitor is effective in suppress- ing resistor noise for frequencies down to 1khz. larger capacitors extend this suppression to proportionately lower frequencies. this issue does not arise in symmetri- cal dual supply applications (figure 2) because agnd goes directly to ground. in applications requiring an analog ground reference other than halfway between the supply rails, the user can over- ride the built-in analog ground reference by tying the agnd pin to a reference voltage within the agnd voltage range specified in the electrical characteristics table. the agnd pin will load the external reference with approxi- mately 5k returned to the mid-supply potential. agnd should still be capacitively bypassed to a ground plane as noted above. do not connect the agnd pin to the v C pin. in (pin 3): analog input. the input signal to the amplifier in the ltc6910-x is the voltage difference between the in and agnd pins. the in pin connects internally to a digitally controlled resistance whose other end is a current sum- ming point at the same potential as the agnd pin (fig- ure 4). at unity gain (digital input 001), the value of this input resistance is approximately 10k w and the in voltage range is rail-to-rail (v + to v C ). at gain settings above unity (digital input 010 or higher), the input resistance falls. also, the linear input voltage range falls in inverse propor- tion to gain. (the higher gains are designed to boost lower level signals with good noise performance.) tables 1, 2, and 3 summarize this behavior. in the zero gain state (digital input 000), analog switches disconnect the in pin internally and this pin presents a very high input resis- tance. the input may vary from rail to rail in the zero gain setting but the output is insensitive to it and remains at the agnd potential. circuitry driving the in pin must consider the ltc6910-xs input resistance and the variation of this resistance when used at multiple gain settings. signal sources with significant output resistance may introduce a gain error as the sources output resistance and the ltc6910-xs input resistance form a voltage divider. this is especially true at the higher gain settings where the input resistance is lowest. in single supply voltage applications at elevated gain settings (digital input 010 or higher), it is important to remember that the ltc6910-xs dc ground reference for both input and output is agnd, not v C . with increasing gains, the ltc6910-xs input voltage range for unclipped output is no longer rail-to-rail but shrinks toward agnd. the out pin also swings positive or negative with respect to agnd. at unity gain (digital input 001), both in and out voltages can swing from rail to rail (tables 1, 2, 3).
ltc6910-1 ltc6910-2/ltc6910-3 16 6910123fa v C , v + (pins 4, 8): power supply pins. the v + and v C pins should be bypassed with 0.1 m f capacitors to an adequate analog ground plane using the shortest possible wiring. electrically clean supplies and a low impedance ground are important for the high dynamic range available from the ltc6910-x (see further details under agnd). low noise linear power supplies are recommended. switching power supplies require special care to prevent switching noise coupling into the signal path, reducing dynamic range. g0, g1, g2 (pins 5, 6, 7): cmos-level digital gain- control inputs. g2 is the most significant bit (msb). these pins control the voltage gain from in to out pins (see uu u pi fu ctio s table 1, table 2 and table 3). digital input code 000 causes a zero gain with very low output noise. in this zero gain state the in pin is disconnected internally, but the out pin remains active and forced by the internal op amp to the voltage present on the agnd pin. note that the voltage gain from in to out is inverting: out and in pins always swing on opposite sides of the agnd potential. the g pins are high impedance cmos logic inputs and must be connected (they will float to unpredictable voltages if open circuited). no speed limitation is associated with the digital logic because it is memoryless and much faster than the analog signal path.
ltc6910-1 ltc6910-2/ltc6910-3 17 6910123fa functional description the ltc6910 family are small outline, wideband inverting dc amplifiers whose voltage gain is digitally program- mable. each delivers a choice of eight voltage gains, controlled by the 3-bit digital inputs to the g pins, which accept cmos logic levels. the gain code is always mono- tonic; an increase in the 3-bit binary number (g2 g1 g0) causes an increase in the gain. table 1, table 2 and table 3 list the nominal voltage gains for ltc6910-1, ltc6910-2 and ltc6910-3 respectively. gain control within each amplifier occurs by switching resistors from a matched array in or out of a closed-loop op amp circuit using mos analog switches (figure 4). bandwidth depends on gain setting. curves in the typical performance characteristics section show measured frequency responses. digital control logic levels for the ltc6910-x digital gain control inputs (pins 5, 6, 7) are nominally rail-to-rail cmos. logic 1 is v + , logic 0 is v C or alternatively 0v when using 5v supplies. the part is tested with the values listed in the electrical characteristics table (digital input high and low volt- ages), which are 10% and 90% of full excursion on the inputs. that is, the tested logic levels are 0.27v and 2.43v with a 2.7v supply, 0.5v and 4.5v levels with 0v and 5v supply rails, and 0.5v and 4.5v logic levels at 5v sup- plies. do not attempt to drive the digital inputs with ttl logic levels (such as hct or ls logic), which normally do not swing near +5v. ttl sources should be adapted with cmos drivers or suitable pull-up resistors to 5v so that they will swing to the positive rail. timing constraints settling time in the cmos gain-control logic is typically several nanoseconds and faster than the analog signal path. when amplifier gain changes, the limiting timing is analog, not digital, because the effects of digital input changes are observed only through the analog output (figure 4). the ltc6910-xs logic is static (not latched) and therefore lacks bus timing requirements. however, as with any programmable-gain amplifier, each gain change causes an output transient as the amplifiers output moves, with finite speed, toward a differently scaled version of the input signal. varying the gain faster than the output can settle produces a garbled output signal. the ltc6910-x analog path settles with a characteristic time constant or time scale, t , that is roughly the standard value for a first order band limited response: t = 1 / (2 p f -3db ), where f -3db is the C3db bandwidth of the amplifier. for example, when the upper C3db frequency is 1mhz, t is about 160ns. the bandwidth, and therefore t , varies with gain (see frequency response and C3db bandwidth curves in typical performance characteristics). after a gain change it is the new gain value that determines the settling time constant. exact settling timing depends on the gain change, the input signal and the possibility of slew limiting at the output. however as a basic guideline, the range of t is 20ns to 1400ns for the ltc6910-1, 20ns to 900ns for the ltc6910-2 and 20ns to 120ns for the ltc6910-3. these numbers correspond to the ranges of C3db bandwidth in the plots of that title under typical performance character- istics. offset voltage vs gain setting the electrical tables list dc offset (error) voltage at the inputs of the internal op-amp in figure 4, v os(oa) , which is the source of dc offsets in the ltc6910-x. the tables also show the resulting, gain dependent offset voltage referred to the in pin, v os(in) . these two measures are related through the feedback/input resistor ratio, which equals the nominal gain-magnitude setting, g: v os(in) = (1 + 1/g) v os(oa) offset voltages at any gain setting can be inferred from this relationship. for example, an internal offset v os(oa) of 1mv will appear referred to the in pin as 2mv at a gain setting g of 1, or 1.5mv at a gain setting of 2. at high gains, v os(in) approaches v os(oa) . (offset voltage can be of either polarity; it is a statistical parameter centered on zero.) the mos input circuitry of the internal op amp in figure 4 draws negligible input currents (unlike some op amps), so only v os(oa) and g affect the overall amplifiers offset. applicatio s i for atio wu uu
ltc6910-1 ltc6910-2/ltc6910-3 18 6910123fa v cc 5v 1 f 500 6910 f05b agnd ltc6910-x 2 4 8 17.4k 17.4k offset nulling and drift because internal op amp offset voltage v os(oa) is gain independent as noted above, offset trimming can be readily added at the agnd pin, which drives the noninverting input of the internal op amp. such a trim shifts the agnd voltage slightly from the systems analog ground refer- ence, where agnd would otherwise connect directly. this is convenient when a low resistance analog ground poten- tial or analog ground reference exists, for the return of a voltage divider as in figure 5a. when adjusted for zero dc output voltage when the ltc6910-x has zero dc input voltage, this dc nulling will hold at other gain settings also. figure 5a shows the basic arrangement for dual-supply applications. a voltage divider (r1 and r2) scales external reference voltages +v ref and Cv ref to a range equaling or slightly exceeding the approximately 10mv op amp off- set-voltage range. resistor r1 is chosen to drop the 10mv maximum trim voltage when the potentiometer is set to either end. thus if v ref is 5v, r1 should be about 100 w . note also that the two internal 10k resistors in figure 4 tend to bias agnd toward the mid-point of v + and v C . the external voltage divider will swamp this effect if r1 is much less than 5k w . when considering the effect of the internal 10k resistors, note that they form a thvenin equivalent of 5k in series with an open-circuit voltage at the halfway potential (v + + v C )/ 2. (although tightly matched, these internal 10k resistors also have an absolute toler- ance of up to 30% and a temperature coefficient of typically C30ppm/ c.) also, as described under pin func- tions for agnd, a bypass capacitor c1 is always advisable when agnd is not connected directly to a ground plane. with this trim technique in place, the remaining dc offset sources are drifts with temperature (typically 6 m v/ c referred to v os(oa) ), shifts in the ltc6910-xs supply voltage divided by the psrr factors, supply voltage shifts coupling through the two 10k internal resistors of figure 4, and of course any shifts in the reference voltages that supply +v ref and Cv ref in figure 5a. figure 5b illustrates how to make an offset voltage adjust- ment relative to the mid-supply potential in single supply applications. resistor values shown provide at least a 10mv adjustment range assuming the minimum values for the internal resistors at pin 2 and a supply potential of 5v. for single supply systems where all circuitry is dc referenced to some other fixed bias potential, an offset adjustment scheme is shown in figure 5c. a low value for r1 overrides the internal resistors at pin 2 and applies the system dc bias to the ltc6910. actual values for the adjustment components depend on the magnitude of the dc bias voltage. offset adjustment component values shown are an example with a single 5v v cc supply and a 1.25v system dc reference voltage. figure 5a. offset nulling (dual supplies) applicatio s i for atio wu uu r2 49.9k c1 3 1 f analog ground reference 20k r1 6910 f05a agnd Cv ref +v ref ltc6910-x 2 figure 5b. offset nulling (single supply, half supply reference) figure 5c. offset nulling (single supply, external reference) v cc 5v v cc 5v 1.25v system dc reference voltage 1 f 500 6910 f05c agnd ltc6910-x 2 4 8 976 4.64k r1 100
ltc6910-1 ltc6910-2/ltc6910-3 19 6910123fa analog input and dc levels as described in tables 1, 2 and 3 and under pin functions, the in pin presents a variable input resistance returned internally to a potential equal to that at the agnd pin (within a small offset-voltage error). this input resistance varies with digital gain setting, becoming infinite (open circuit) at zero gain (digital input 000), and as low as 1k w at high gain settings. it is important to allow for this input-resistance variation with gain, when driving the ltc6910-x from other circuitry. also, as the gain in- creases above unity, the dc linear input-voltage range (corresponding to rail-to-rail swing at the out pin) shrinks toward the agnd potential. the output swings positive or negative around the agnd potential (in the opposite direction from the input, because the gain is inverting). ac-coupled operation adding a capacitor in series with the in pin makes the ltc6910-x into an ac-coupled amplifier, suppressing the sources dc level (and even minimizing the offset voltage from the ltc6910-x itself). no further components are required because the input of the ltc6910-x biases itself correctly when a series capacitor is added. the in pin connects to an internal variable resistor (and floats when dc open-circuited to a well defined voltage equal to the agnd input voltage at nonzero gain settings). the value of this internal input resistor varies with gain setting over a total range of about 1k to 10k, depending on version (the rightmost columns of table 1, table 2 and table 3). therefore, with a series input capacitor the low frequency cutoff will also vary with gain. for example, for a low frequency corner of 1khz or lower, use a series capacitor of 0.16 m f or larger. a 0.16 m f capacitor has a reactance of 1k w at 1khz, giving a 1khz lower C3db frequency for gain settings of 10v/v through 100v/v in the ltc6910-1. if the ltc6910-1 is operated at lower gain settings with an 0.16 m f input capacitor, the higher input resistance will reduce the lower corner frequency down to 100hz at a gain setting of 1v/v. these frequencies scale inversely with the value of the input capacitor. note that operating the ltc6910-x in zero gain mode (digital inputs 000) open circuits the in pin and this demands some care if employed with a series input capacitor. when the chip enters the zero gain mode, the opened in pin tends to freeze the voltage across the capacitor to the value it held just before the zero gain state. this can place the in pin at or near the dc potential of a supply rail (the in pin may also drift to a supply potential in this state due to small junction leakage currents). to prevent driving the in pin outside the supply limit and potentially damaging the chip, avoid ac input signals in the zero gain state with a series capacitor. also, switching later to a nonzero gain value will cause a transient pulse at the output of the ltc6910-x (with a time constant set by the capacitor value and the new ltc6910-x input resis- tance value). this occurs because the in pin returns to the agnd potential and transient current flows to charge the capacitor to a new dc drop. snr and dynamic range the term dynamic range is much used (and abused) with signal paths. signal-to-noise ratio (snr) is an unam- biguous comparison of signal and noise levels, measured in the same way and under the same operating conditions. in a variable gain amplifier, however, further characteriza- tion is useful because both noise and maximum signal level in the amplifier will vary with the gain setting, in general. in the ltc6910-x, maximum output signal is independent of gain (and is near the full power supply voltage, as detailed in the swing sections of the electrical characteristics table). the maximum input level falls with increasing gain, and the input-referred noise falls as well (as listed also in the table). to summarize the useful signal range in such an amplifier, we define dynamic range (dr) as the ratio of maximum input (at unity gain) to minimum input-referred noise (at maximum gain). (these two num- bers are measured commensurately, in rms volts. for deterministic signals such as sinusoids, 1v rms = 2.828v p-p .) this dr has a physical interpretation as the range of signal levels that will experience an snr above unity v/v or 0db. at a 10v total power supply, dr in the ltc6910-1 (gains 0v to 100v/v) is typically 120db (the ratio of a nominal 9.9v p-p , or 3.5v rms , maximum input to the 3.4 m v rms high gain input noise). the corresponding dr for the ltc6910-2 (gains 0v to 64v) is also 120db; for applicatio s i for atio wu uu
ltc6910-1 ltc6910-2/ltc6910-3 20 6910123fa typical applicatio s u the ltc6910-3 (gains 0v to 7v/v) it is 117db. the snr from an amplifier is the ratio of input level to input- referred noise, and can be 110db with the ltc6910 family at unity gain. construction and instrumentation cautions electrically clean construction is important in applications seeking the full dynamic range of the ltc6910-x ampli- fier. short, direct wiring will minimize parasitic capaci- tance and inductance. high quality supply bypass capaci- tors of 0.1 m f near the chip provide good decoupling from a clean, low inductance power source. but several cm of wire (i.e., a few microhenrys of inductance) from the power supplies, unless decoupled by substantial capaci- tance ( 3 10 m f) near the chip, can cause a high-q lc resonance in the hundreds of khz in the chips supplies or ground reference. this may impair circuit performance at those frequencies. a compact, carefully laid out printed circuit board with a good ground plane makes a significant difference in minimizing distortion. finally, equipment to measure amplifier performance can itself introduce distortion or noise floors. checking for these limits with a wire replacing the chip is a prudent routine procedure. expanding an adcs dynamic range figure 6 shows a compact data acquisition system for wide ranging input levels. this figure combines an ltc6910-x programmable amplifier (8-lead tsot-23) with an ltc1864 analog-to-digital converter (adc) in an 5 1 499 270pf ltc1864 3 v in agnd gain control 1 f 6910 f04 6 4 ltc6910-x 7 8 5v 0.1 f 2 1 f adc control v ref in + in C gnd 5v v cc sck sdo conv figure 6. expanding an adcs dynamic range 8-lead msop. this adc has 16-bit resolution and a maxi- mum sampling rate of 250ksps. an ltc6910-1, for ex- ample, expands the adcs input amplitude range by 40db while operating from the same single 5v supply. the 499 w resistor and 270pf capacitor couple cleanly between the ltc6910-xs output and the switched-capacitor input of the ltc1864. the 270pf capacitor should be an npo or x7r type, and lead length and inductance in the connec- tions to the ltc1864 inputs must be minimized, to achieve the full performance capability of this circuit. (see ltc 1864 data sheet for further general information.) at a gain setting of 10v/v in an ltc6910-1 (digital input 100) and a 250ksps sampling rate in the ltc1864, a 10khz input signal at 60% of full scale shows a thd of C87db at the digital output of the adc. 100khz input signals under the same conditions produce thd values around C 75db. noise effects (both random and quantiza- tion) in the adc are divided by the gain of the amplifier when referred to v in in figure 4. because of this, the circuit can acquire a signal that is 40db down from full scale of 5v p-p with an snr of over 70db. such performance from an adc alone (70 + 40 = 110db of useful dynamic range at 250ksps), if available, would be far more expensive. low noise ac amplifier with programmable gain and bandwidth analog data acquisition can exploit band limiting as well as gain to suppress unwanted signals or noise. tailoring an analog front end to both the level and bandwidth of each source maximizes the resulting snr.
ltc6910-1 ltc6910-2/ltc6910-3 21 6910123fa typical applicatio u figure 7 shows a block diagram and figure 8 the practical circuit for a low noise amplifier with gain and bandwidth independently programmable over 100:1 ranges. one ltc6910-x controls the gain and another controls the bandwidth. an lt1884 dual op amp forms an integrating lowpass loop with capacitor c2 to set the programmable upper corner frequency. the lt1884 also supports rail-to- rail output swings over the total supply voltage range of 2.7v to 10.5v. ac coupling through capacitor c1 estab- + + + + v in c1 gain control pga (gain a) v out = (gain a)v in bandwidth control pga (gain b) gain = ? c2 r1 r2 v out 6910 f05 1 2 r1c1 bandwidth 1 r2 (gain b) 2 c2 figure 7. block diagram of an ac amplifier with programmable gain and bandwidth lishes a fixed low frequency corner of 1hz, which can be adjusted by changing c1. alternatively, shorting c1 makes the amplifier dc coupled. (if dc gain is not needed, however, the ac coupling suppresses several error sources: any shifts in dc levels, low frequency noise and all amplifier dc offset voltages other than the low internally trimmed lt1884 offset in the integrating amplifier. if desired, another coupling capacitor in series with the input can relax the requirements on dc input level as well.)
ltc6910-1 ltc6910-2/ltc6910-3 22 6910123fa + C + C 8 7 6 5 v C v out r4 15.8k v C v + v + lt1884 c2 1 f c1 10 f r1 15.8k 2 7 8 3 v in 6 4 5 1 r2 15.8k 0.1 f gn2 gn1 gn0 0 0 1 gain = 1 0 1 0 gain = 2 0 1 1 gain = 5 1 0 0 gain = 10 1 0 1 gain = 20 1 1 0 gain = 50 1 1 1 gain = 100 bw2 bw1bw0 bandwidth 1hz to 10hz 0 0 1 bandwidth 1hz to 20hz 0 1 0 bandwidth 1hz to 50hz 0 1 1 bandwidth 1hz to 100hz 1 0 0 bandwidth 1hz to 200hz 1 0 1 bandwidth 1hz to 500hz 1 1 0 bandwidth 1hz to 1000hz 1 1 1 0.1 f 0.1 f v + v C 1 2 3 4 2 7 8 3 6 4 5 1 0.1 f 0.1 f 0.1 f v + v C ltc6910-1 ltc6910-1 r3 15.8k bandwidth control gain control frequency (hz) ?0 gain (db) ?0 ?0 ?0 0 10 1 100 1k 100k 6910 f06b ?0 10 10k ?0 ?0 ?0 gn2 gn1 gn0 = 001 bw2 1 bw1 0 bw0 0 bw2 0 bw1 0 bw0 1 bw2 1 bw1 1 bw0 1 gain vs frequency figure 8. low noise ac amplifier with programmable gain and bandwidth typical applicatio s u measured frequency responses in figure 8 with ltc6910-1 pgas demonstrate bandwidth settings of 10hz, 100hz and 1khz, with digital codes at the bw inputs of respectively 001, 100 and 111, and unity gain in each case. by scaling c2, this circuit can serve other bandwidths, such as a maximum of 10khz with 0.1 m f using lt1884 (gain-bandwidth product around 1mhz). noise floor from internal sources yields an output snr of 76db with 10mv p- p input, gain of 100 and 100hz bandwidth; for 100mv p-p input, gain of 10 and 1000hz bandwidth it is 64db.
ltc6910-1 ltc6910-2/ltc6910-3 23 6910123fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio 1.50 ?1.75 (note 4) 2.80 bsc 0.22 ?0.36 8 plcs (note 3) datum ? 0.09 ?0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 3.85 max 0.52 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637)
ltc6910-1 ltc6910-2/ltc6910-3 24 6910123fa part number description comments lt ? 1228 100mhz gain controlled transconductance amplifier differential input, continuous analog gain control lt1251/lt1256 40mhz video fader and gain controlled amplifier two input, one output, continuous analog gain control ltc1564 10khz to 150khz digitally controlled filter and pga continuous time, low noise 8th order filter and 4-bit pga ltc6911 dual matched programmable gain amplifier dual 6910 in a 10 lead msop ltc6915 zero drift instrumentation amplifier with programmable gain zero drift, digitally programmable gain up to 4096 v/v linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2002 lt/tp 0404 1k rev a ? printed in usa related parts typical applicatio u 2 1 3 v in v out = gain ?v in agnd 1 f or larger pin 2 (agnd) sets dc output voltage and has built-in half-supply reference with internal resistance of 5k. agnd can also be driven by a system analog ground reference near half supply c1 value sets lower corner frequency. the table shows this frequency with c1 = 1 f. this frequency scales inversely with c1 6910 ta02 5 4 ltc6910-x 6 8 v + 2.7v to 10.5v 0.1 f g2 g1 g0 7 c1 0 ? ? ? ?0 ?0 ?0 100 0 ? ? ? ? ?6 ?2 ?4 ltc6910-1 ltc6910-2 ltc6910-3 0 ? ? ? ? ? ? ? passband gain passband gain passband gain lower ?db freq (c1 = 1 f ) lower ?db freq (c1 = 1 f ) lower ?db freq (c1 = 1 f ) 16hz 32hz 80hz 160hz 160hz 160hz 160hz 16hz 32hz 64hz 127hz 127hz 127hz 127hz 16hz 32hz 48hz 64hz 80hz 95hz 111hz digital inputs 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 g2 g1 g0 ac-coupled single supply amplifiers frequency response, ltc6910-1 frequency (hz) 100 ?0 gain (db) 0 10 20 30 40 50 1k 10k 100k 1m 6910 ta03 g2, g1, g0 = 111 g2, g1, g0 = 110 g2, g1, g0 = 101 g2, g1, g0 = 100 g2, g1, g0 = 011 g2, g1, g0 = 010 g2, g1, g0 = 001 v s = 10v, v in = 5mv rms c1 = 1 f frequency response, ltc6910-2 frequency (hz) 100 ?0 gain (db) 0 10 20 30 40 1k 10k 100k 1m 6910 ta04 v s = 10v, v in = 5mv rms c1 = 1 f g2, g1, g0 = 111 g2, g1, g0 = 110 g2, g1, g0 = 101 g2, g1, g0 = 100 g2, g1, g0 = 011 g2, g1, g0 = 010 g2, g1, g0 = 001 frequency response, ltc6910-3 frequency (hz) 10 100 ?0 gain (db) ? 0 5 10 15 20 1k 10k 100k 10m 1m 6910 ta05 g2, g1, g0 = 111 g2, g1, g0 = 110 g2, g1, g0 = 101 g2, g1, g0 = 100 g2, g1, g0 = 011 g2, g1, g0 = 010 g2, g1, g0 = 001 v s = 10v v in = 10mv rms c1 = 1 f

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